In the arrangement of DRAM cell processing using a shallow trench isolation region to realize a small-size capacitor, gate oxide reliability of support oxides is limited by the thickness of the gate oxide at the AA (active area) corners. Therefore, careful optimization of the AA oxidation, (sacrificial) oxide, and oxidation is necessary to create the required AA corner rounding and the oxide thickness at the AA corner. In fact, in all too many instances, the oxide is thinner at the corners than at the AA area.
U.S. Pat. No. 5,330,920 discloses a method of controlling gate oxide thickness in the fabrication of semiconductor devices. In this process a sacrificial gate oxide layer is formed on select locations of a semiconductor substrate surface. Nitrogen ions are implanted into the select locations of the substrate through the sacrificial gate oxide layer. The substrate and sacrificial gate oxide layer are thermally annealed to assist pile-up of the nitrogen ions at the semiconductor substrate surface. The sacrificial gate oxide layer is removed and a gate oxide layer is thermally formed on the silicon semiconductor substrate surface. The select locations having nitrogen ion implanted will have a thinner gate oxide layer than a non-implanted region.
Fabrication of an integrated device using nitrogen implantation is disclosed in U.S. Pat. No. 6,037,639. In this process, a channel region is defined by a source and drain region of a semiconductor substrate. A gate structure includes an isolating oxide layer positioned on the channel region and a polysilicon layer positioned on the oxide layer. More specifically, the process includes the step of forming the nitrogen implanted regions over the semiconductor substrate by implanting nitrogen atoms into those regions and growing spacers from exposed portions of the polysilicon layer. During the spacer growth, the spacer grows vertically as well as laterally extending under the polysilicon edges. Diffusion of nitrogen atoms to the substrate surface forms silicon nitride under the gate edges, which minimizes current leakages into the gate polysilicon.
U.S. Pat. No. 5,920,779 discloses a process for differential gate oxide thickness by nitrogen implantation for mixed mode and embedded VLSI circuits. A semiconductor substrate has a surface and includes a first region on which a plurality of first MOS devices are to be formed and a second region on which a plurality of second MOS devices are to be formed. The second region is masked and a first concentration of a first dopant is provided in the semiconductor substrate at the surface of the first region without doping the second region. The mask is then removed from over the second region. The first region is masked and a second concentration of a second dopant is provided in the semiconductor substrate at the surface of the second region without doping the first region. The second concentration is different than the first concentration. The surface of the semiconductor substrate is oxidized to grow a first thickness of oxide on the first region of the semiconductor substrate and to grow a second, different thickness of oxide on the second region in a single oxidizing process. First MOS devices are formed on the first regions of the semiconductor substrate incorporating the first thickness of oxide and second MOS devices are formed on the second region incorporating the second thickness of oxide. The first and second dopants are both nitrogen and the first concentration is greater than the second concentration.
In general, a typical way to achieve two oxide thicknesses in one oxidation step is to make use of local nitrogen implantation to reduce the oxidation rate at the implanted sites. The use of local nitrogen implementation to achieve two oxidation thicknesses in one oxidation step consists of utilizing the process integration scheme that includes growing of a sacrificial oxide. Dopants are implanted through the sacrificial oxide. A photoresist mask is employed to pattern an integrated circuit that includes the first transistor having a first dielectric thickness and a second transistor having a second dielectric thickness. Nitrogen ions are implanted to create dual gate oxide devices. The photoresist mask and the sacrificial oxide are stripped off and the gate is subjected to oxidation.
Due to the fact that, in many cases, the gate oxide reliability of support oxide is limited by the thickness of the gate oxide at the AA (active area) corners, and careful optimization of AA oxidation, sacrificial oxide, and gate oxidation is necessary to create the required AA corner rounding and the oxide thickness at the AA corner, there is a need to limit the dual gate nitrogen dose in the AA to the inner part of the gate area to provide increased gate oxide thickness at the active area corner and thereby increase the threshold of the parasitic corner device, reduce sub-threshold voltage (Vt) and junction leakage.